岗位职责: Responsibilities: 1.在FPGA平台上实现RTL的prototype，用于系统演示以及芯片前的模拟/验证； Implement the RTL prototype on FPGA platform for system demonstration as well as pre-silicon emulation/verification. 2.使用Verilog HDL进行FPGA RTL设计，使用Synplify/Vivado软件工具进行Synthesis/PAR/ timing； FPGA RTL design with Verilog HDL, Synthesis/PAR/timing closure with Synplify/Vivado. 3.基于ASIC设计的FPGA开发流程创建和文档编制； FPGA development flow creation and documentation based on ASIC design. 4.基于PL+PS的架构，开发和调试基于包括LVDS/Aurora/PCIe/Ethernet等接口的Dump和HIL数据功能的开发 Develop and debug dump and HIL data functions RTL based on interfaces including LVDS, Aurora, PCIe, and Ethernet using a PL+PS architecture FPGA. 5.对自己负责的模块由软件驱动编写和调试的能力，验证其功能符合设计预期 5.Ability to write and debug software-driven code for assigned modules, verifying that their functionality meets design expectations 6.与软/硬件团队进行板载调试； Onboard debugging with HW/SW team. 7.制定下一代FPGA/HW平台的要求(包括设备容量和接口以及相关的调试/附加硬件/子卡)。 Specify requirements for the next generation FPGA/HW platform (including device capacity and interfaces and associated debug/add-on hardware/daughter-cards). 岗位要求： Requirements： 1.本科学历，硕士优先； Bachelor required, and Master preferred. 2.至少有一年FPGA开发验证的经验； At least one years of experience in development and verification on FPGA. 3.FPGA工具链(RTL, P&R，时序分析/收敛，功率分析等)； FPGA tool chain (RTL, P&R, timing analysis/closure, power analysis, etc.). 4.熟练掌握大规模RTL设计、逻辑仿真和实现； Expert level proficiency with RTL design modification, logic simulation and implementation tools for large complex designs. 5.熟悉FPGA时序和FPGA (Cyclone/Zynq/VirtexUltraScale)架构/时钟系统； Good understanding of FPGA timing and FPGA (Cyclone/Zynq/VirtexUltraScale) architecture/clock system. 6.熟悉常用的仿真工具，编程工具，具有一定基础的嵌入式开发能力； Familiar with common simulation tools and programming tools, and possess a certain level of basic embedded development capabilities. 7.熟悉常用的实验室设备和工具； Familiarity with common lab equipment and tools. 8.具有良好的表达和书面沟通能力，能较好的与各职能部门沟通； Good verbal and written communication skills and communicates well across functional groups. 9.有无线通信SoC方面经验者优先； Experience in wireless communication SoC is a plus. 10.有雷达系统方面经验者优先。 Experience in radar system is a plus.