Job Responsibility: 岗位职责： 1. Analyze NPU hardware architecture and design specifications, decompose verification functional points, and compile complete module-level and subsystem-level verification plans 研读NPU硬件架构与设计规格文档，拆解验证功能点，编写模块级、子系统级完整验证计划 2. Build and maintain reusable UVM verification environments for NPU core modules, including pipeline control, data calculation, weight/activation data interaction, multi-producer multi-consumer data transmission and timing handshake logic. 搭建、维护可复用的NPU核心模块UVM验证环境，覆盖流水线控制、数据运算、权重/激活值数据交互、多生产者多消费者数据传输、时序握手等核心逻辑 3. Develop directed and constrained random test cases, complete functional simulation, regression testing, and locate, analyze and fix RTL functional bugs in cooperation with design engineers. 开发定向测试用例与约束随机测试用例，完成功能仿真与回归测试，配合设计工程师定位、分析并修复RTL功能缺陷 4. Complete code coverage and functional coverage collection, analysis and closure, continuously optimize verification scenarios, and ensure full verification of NPU core functions and boundary scenarios 完成代码覆盖率、功能覆盖率的收集、分析与收敛，持续补充验证场景，保障NPU核心功能、边界场景全覆盖验证 5. Verify mainstream AI algorithm hardware implementations, including CNN, Transformer, matrix multiplication, convolution pooling and other neural network operator hardware logic. 负责主流AI算法硬件实现逻辑验证，涵盖CNN、Transformer、矩阵乘、卷积池化等各类神经网络算子硬件通路验证 6. Collaborate with system architects, RTL designers, software development and physical implementation teams to solve cross-module and cross-stage verification problems, support tape-out and post-silicon verification. 协同系统架构师、RTL设计、软件开发、物理实现团队，解决跨模块、跨阶段验证问题，支撑芯片流片及回片验证工作 7. Optimize verification efficiency, improve regression framework, compress simulation time, and sort out verification technical documents and experience precipitation. 持续优化验证效率，迭代回归测试框架，精简仿真耗时，完成验证技术文档编写与技术经验沉淀 Job Requirements: 任职要求： 1. Bachelor or above degree in Microelectronics, Electronic Engineering, Computer Science and other related majors, IC design verification experience, with independent NPU/AI chip verification experience. 微电子、电子工程、计算机等相关专业本科及以上学历，有 IC设计验证工作经验，有独立NPU/AI芯片验证实战经验 2. Proficient in Verilog/SystemVerilog, master UVM verification methodology, independently capable of building module/subsystem-level verification environments and completing full verification flow. 熟练掌握Verilog/SystemVerilog语言，精通UVM验证方法学，可独立搭建模块/子系统验证环境，完整走完验证全流程 3. Familiar with NPU core hardware architecture, master the verification principles of convolution operation, matrix multiplication, data scheduling, pipeline transmission, memory access and other core modules. 熟悉NPU核心硬件架构，掌握卷积运算、矩阵乘运算、数据调度、流水线传输、访存通路等核心模块的验证原理与方法 4. Understand basic principles of neural network algorithms (CNN/Transformer), familiar with common AI operator hardware implementation logic. 了解CNN、Transformer等主流神经网络算法基础原理，熟悉常用AI算子的硬件实现逻辑 5. Familiar with mainstream EDA tools: VCS, Verdi, Coverage tool, proficient in constrained random verification, assertion checking and bug debugging. 熟练使用VCS、Verdi、覆盖率分析等主流EDA工具，精通约束随机验证、断言检查、波形调试与问题定位 6. Familiar with IC verification complete flow from specification sorting, verification planning, environment building, case development to coverage closure. 熟悉从规格梳理、验证方案制定、环境搭建、用例开发到覆盖率收敛的完整IC验证流程 7. Good logical thinking, hands-on ability and team collaboration ability, able to independently undertake module and subsystem verification tasks. 逻辑思维清晰，动手能力强，具备良好的团队协作能力，可独立承接模块及子系统验证任务 Job Location: Shanghai,/Shenzhen 工作地点：上海/深圳