Job Responsibility: 岗位职责： Job Responsibility: 岗位职责： 1. Physical Design Implementation: Participate in the RTL-to-GDSII physical design flow for advanced SoC/IP designs, including floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, and design optimization. 数字后端物理实现： 参与先进工艺 SoC/IP 的 RTL-to-GDSII 数字后端设计流程，包括 Floorplan、电源规划（Power Planning）、布局（Placement）、时钟树综合（CTS）、布线（Routing）及设计优化。 2. Timing Analysis & Closure: Perform Static Timing Analysis (STA), analyze setup/hold timing violations, and work with design teams to achieve timing closure across different operating modes and PVT corners. 时序分析与收敛： 参与静态时序分析（STA），分析 Setup/Hold 等时序违例，并配合设计团队完成不同工作模式及 PVT Corner 下的时序收敛。 3. PPA Optimization: Analyze and optimize Performance, Power, and Area (PPA) throughout the physical design flow, including placement, clock, timing, congestion, and power-related optimization. PPA 优化： 在物理设计过程中分析并优化芯片性能、功耗和面积（Performance, Power and Area），参与 Placement、Clock、Timing、Congestion 及 Power 等相关优化工作。 4.Physical Verification & Signoff: Participate in physical design signoff activities, including DRC/LVS, parasitic extraction, signal integrity, and EM/IR analysis, to ensure designs meet timing, power, reliability, and foundry requirements. 物理验证与 Signoff： 参与 DRC/LVS、寄生参数提取（RC Extraction）、信号完整性（SI）及 EM/IR 等物理验证与 Signoff 工作，确保设计满足时序、功耗、可靠性及 Foundry 设计规则要求。 5.Flow Automation & Cross-Functional Collaboration: Develop scripts and automation utilities to improve design efficiency, and collaborate with RTL, STA, DFT, CAD, verification, and other teams to debug design issues and support successful chip tape-out. 流程自动化与跨团队协作： 编写脚本及自动化工具提升设计效率，并与 RTL、STA、DFT、CAD、验证等团队协作，分析和解决设计问题，支持芯片顺利完成 Tape-out。 Job Requirements: 任职要求: 1. Master’s degree or above in Microelectronics, Integrated Circuit Design, Electronic Engineering, Computer Engineering, Computer Science, or related fields). 微电子、集成电路设计、电子工程、计算机工程、计算机科学或相关专业，硕士及以上学历。 2. Solid understanding of digital IC fundamentals, CMOS circuits, and the ASIC design flow; basic understanding of the RTL-to-GDSII physical design flow. 具备扎实的数字集成电路、CMOS 电路及 ASIC 设计基础，了解从 RTL 到 GDSII 的数字后端设计基本流程。 3. Solid understanding of digital timing concepts, including setup/hold time, clock skew, clock latency, transition, and basic Static Timing Analysis (STA) concepts. 掌握数字电路时序基本概念，包括 Setup/Hold Time、Clock Skew、Clock Latency、Transition 等，并具备基本的静态时序分析（STA）知识. 4. Basic knowledge of physical design concepts such as floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification. 了解 Floorplan、Placement、Clock Tree Synthesis、Routing、Timing Closure 和 Physical Verification 等数字后端基本概念. 5. Familiar with at least one mainstream EDA physical design or timing analysis tool, such as Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/ICC2/Design Compiler/PrimeTime. 熟悉至少一种主流数字后端或时序分析 EDA 工具，如 Cadence Innovus/Genus/Tempus，或 Synopsys Fusion Compiler/ICC2/Design Compiler/PrimeTime. 6. Familiar with the Linux environment and proficient in at least one scripting language such as Tcl, Python, Perl, or Shell. 熟悉 Linux 开发环境，至少掌握一种脚本语言，如 Tcl、Python、Perl 或 Shell。 7. Strong analytical and problem-solving skills, with the ability to learn new technologies and debug complex engineering problems; good communication and teamwork skills. 具备较强的逻辑分析、问题定位和解决能力，能够快速学习新技术并分析复杂工程问题，同时具备良好的沟通能力和团队协作能力。 Preferred Qualifications 加分项： 1. Internship, research, coursework, or project experience related to ASIC Physical Design, RTL-to-GDSII implementation, STA, or chip tape-out is highly preferred. 具有 ASIC 数字后端、RTL-to-GDSII、STA 相关实习、科研、课程设计或芯片流片项目经验者优先。 2. Hands-on experience with mainstream EDA tools such as Innovus, Fusion Compiler/ICC2, PrimeTime/Tempus, Calibre/ICV, StarRC/Quantus, or RedHawk is a plus. 具有 Innovus、Fusion Compiler/ICC2、PrimeTime/Tempus、Calibre/ICV、StarRC/Quantus、RedHawk 等主流 EDA 工具实际使用经验者优先。 3. Good understanding of timing constraints (SDC), multi-clock designs, clock domain crossing, low-power design concepts (UPF), or multi-voltage designs is a plus. 熟悉时序约束（SDC）、多时钟设计、跨时钟域（CDC）、低功耗设计（UPF）或多电压域设计基本概念者优先。 4. Experience in Tcl/Python-based EDA flow automation, data analysis, or development of design productivity tools is a plus. 具有基于 Tcl/Python 的 EDA Flow 自动化、数据分析或设计效率工具开发经验者优先。 Job Location: Shanghai, Shenzhen 工作地点: 上海，深圳